In the design of the bus storage architecture of an application processor (AP) in the prior art, when a central processing unit (CPU) or an input/output (TO) peripheral accesses a low power double data rate 4 dynamic random access memory (LPDDR4 DRAM), four access channels generally need to be accessed in an address interleaving manner, and an interleaving granularity is statically configured.
When a CPU or an IO peripheral accesses a DRAM by using the existing bus storage architecture, there exist the following disadvantages. In some application scenarios (for example, voice conversation or audio playback) in which an AP processes a low bandwidth demand, compared with accessing the DRAM by using a single access channel, accessing the DRAM by using a four-access channel interleaving mode in the prior art has higher power consumption, if a single access channel is reserved for an address space to access the DRAM, address segments, which are parallel to the address space, of the other three access channels cannot be used, when the CPU and the IO device has large (mainly media Internet Protocol) bandwidth traffic in some scenarios, an access channel cannot be isolated in the four-access channel interleaving mode in the prior art, resulting in bus congestion, and in some scenarios, access modes for accessing the DRAM are different in different Internet Protocols (IPs), resulting in communication disparity of the DRAM.